1. Field of the Invention
The present invention relates to volatile memory and, in particular, refers to a method and device for providing a write current for storing a digital logic state in a giant magneto-resistance (GMR) element during a power down event.
2. Description of the Related Art
Since the introduction of the digital computer, electronic storage devices have been a vital resource for the retention of binary data. Conventional electronic storage devices, such as static random access memory (SRAM) and dynamic random access memory (DRAM), have been successfully integrated into computing devices for storing digital information. SRAM storage devices utilize static latch structures as storage cells. Typically, an SRAM latch structure is a complementary metal-oxide semiconductor (CMOS) circuit comprising two cross-coupled inverters, wherein the simultaneous activation of two access transistors regulates the flow of current through the cross-coupled inverter circuits for read and write functions. In addition, DRAM storage devices typically incorporate an inline access transistor and a capacitor type structure that are configured to temporarily store one bit of binary information based on the charged state of the capacitor.
Unfortunately, SRAM and DRAM require a continuous supply of power to maintain a particular defined logic state, and DRAM capacitors further require a periodic charge refresh from the inline access transistor to maintain the particular defined logic-state. Therefore, conventional semiconductor random access memory (RAM) is considered volatile memory due to the fact that data may be lost with the loss or interruption of power.
Preventing the loss of data during power interrupts has its disadvantages. Typical systems utilize a primary power source for normal applications and an auxiliary power source for back-up power in case the primary power source fails. The auxiliary power source may be employed within the system to increase the reliability of conventional memory devices in the event of a power failure. Implementing this approach may be cumbersome and inconvenient in that additional devices and circuitry, including the auxiliary power source and power switching circuitry, may be required. In addition, the auxiliary power source usually comprises a battery or the like that has a finite or limited lifetime. Therefore, if the primary power source fails for an extended period of time, the auxiliary power source may also eventually fail causing the conventional memory devices to lose the logic states or data stored therein due to the extended period of time of the power failure.
In some circumstances, conventional memory devices may be replaced with non-volatile memory devices, such as giant magneto-resistive (GMR) devices, such that volatile logic states may be stored in a non-volatile manner. Although GMR devices may facilitate the adverse effects of losing data during power interrupts, GMR devices typically require a current pulse sufficiently capable of generating orthogonal magnetic fields, which may be difficult to implement during loss of power. Auxiliary power sources may be used to provide enough power for storing logic states in GMR devices, but the additional cost associated with using auxiliary power components may deter the use thereof.
Based on the foregoing, there currently exists a need to replace conventional volatile memory devices and circuitry with improved solid-state non-volatile memory devices and circuitry so as to substantially preserve logic states in a non-destructive manner during an interrupt in power. Furthermore, there also exists a need to develop non-volatile memory devices that may be used in conventional applications without compromising the high-density fabrication and processing techniques.